1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, but not by way of limitation, the present invention relates to a glitch protect valid cell and method for maintaining a desired state value of a true valid bit in response to a glitch signal and a timing signal.
2. Description of the Related Art
Some common semiconductor memory devices, such as a content addressable memory (CAM) device, typically attach a valid cell at the beginning of a row of integrated data storage units. In effect, valid cells grant access for word data to be stored to and retrieved from a row of data storage units according to the logical state value of a true valid bit stored in a valid cell. Typically, access to entry data is granted if the state value of the true valid bit is “valid”, often valued as a logical “1”, and denied if the logic state value of the true valid bit is “invalid”, often valued as a logical “0”.
Illustratively, each word entry in a CAM device features a true valid bit stored in a valid cell. As opposed to other semiconductor devices that first require at least one specific memory address prior to retrieving entry data, CAM semiconductor devices provide high speed data access whereby contents in memory-are accessed through a relatively faster search and match operation scheme. Accordingly, because of their quick and effective search and match capabilities, CAM semiconductor devices with valid cells are often used in high speed switching systems ranging from communication and computer networks to voice and image recognition systems, such as routers, core switches, remote access servers, processor address translation, memory cache hierarchies, and digital-subscriber-line access multiplexers.
Problems may arise, accumulate, and potentially compound if one or many signals for invalidating a true valid bit arrive too late after a typical high speed compare and match operation between the valid cell and CAM array. Unfortunately, there exists no known device that adequately compensates for time delayed invalidate functions, hereinafter referred to as a “glitch signal(s)”, with respect to a true valid bit within a valid cell. In this disclosure and appended claims the term “glitch signal” refers to a signal variance typically in the form of a brief pulse which could possibly trigger a logic state change of a true valid bit. Typically, a signal variance results from a time delay in a combinational logic circuit from the point in time that input signals are applied until their effect propagates through the various components of the combinational logic circuit and resulting outputs react to the inputs.
Therefore, a need exists for a device that is responsive to at least one glitch signal. In particular, there exists a need for a device that restores an initial valid state value of a true valid bit after being subjected to at least one glitch signal. Moreover, there exists a need for a device that maintains an initial invalidate state value of a true valid bit after being subjected to at least one glitch signal. Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as herein described.